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IDT54/74FCT373T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS OCTAL TRANSPARENT LATCH
IDT54/74FCT373T/AT/CT
FEATURES:
* * * *
* * * * *
Std., A, and C grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: - Industrial: SOIC, SSOP, QSOP, TSSOP - Military: CERDIP, LCC
DESCRIPTION:
The FCT373Tis an octal transparent latch built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE is high, the bus output is in the high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D O G
D O G
D O G
D O G
D O G
D O G
D O G
D O G
LE
OE O0 O1 O2 O3 O4 O5 O6 O7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
JUNE 2002
DSC-5496/3
(c) 2002 Integrated Device Technology, Inc.
IDT54/74FCT373T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
VCC
20
O0
OE
O0 D0 D1 O1 O2 D2 D3 O3 GND
2 3 4 5 6 7 8 9 10
19 18 17 16 15 14 13 12 11
O7 D7 D6 O6 O5 D5 D4 O4 LE D1 O1 O2 D2 D3
4 5 6 7 8 9 10 11 12 13 3 2 1 19 18 17 16 15 14
D0
O7
OE
1
20
VCC
INDEX
D7 D6 O6 O5 D5
O3
O4
GND
CERDIP/ SOIC/ SSOP/ QSOP/ TSSOP TOP VIEW
LCC TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max -0.5 to +7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG IOUT Storage Temperature DC Output Current
PIN DESCRIPTION
Pin Names Dx LE OE Ox Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs Description
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only.
FUNCTION TABLE(1)
Dx H L X Inputs LE H H X OE L L H Outputs Ox H L Z
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
NOTE: 1. H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level Z = High Impedance
NOTE: 1. This parameter is measured at characterization but not tested.
2
LE
D4
IDT54/74FCT373T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current (3-State output pins)(4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max., VI = VCC (Max.) VCC = Min, IIN = -18mA -- VCC = Max., VIN = GND or VCC Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V Min. 2 -- -- -- -- -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01 Max. -- 0.8 1 1 1 1 1 -1.2 -- 1 A V mV mA Unit V V A A A
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = Min IOH = -6mA MIL VIN = VIH or VIL IOH = -8mA IND IOH = -12mA MIL IOH = -15mA IND VCC = Min IOL = 32mA MIL VIN = VIH or VIL IOL = 48mA IND VCC = Max., VO = GND(3) VCC = 0V, VIN or VO 4.5V Min. 2.4 2 -- -60 -- Typ.(2) 3.3 3 0.3 -120 -- Max. -- -- 0.5 -225 1 V mA A Unit V
VOL IOS IOFF
Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. This parameter is guaranteed but not tested.
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IDT54/74FCT373T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND One Input Toggling 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle OE = GND LE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle OE = GND LE = VCC Eight Bits Toggling
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz.
Test Conditions(1)
Min. --
Typ.(2) 0.5 0.15
Max. 2 0.25
Unit mA mA/ MHz
VIN = VCC VIN = GND
--
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
1.5
3.5
mA
--
1.8
4.5
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
3
6(5)
mA
--
5
14(5)
4
IDT54/74FCT373T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW Parameter Propagation Delay Dx to Ox Propagation Delay LE to Ox Output Enable Time Output Disable Time Set-up Time HIGH or LOW, Dx to LE Hold Time HIGH or LOW, Dx to LE LE Pulse Width HIGH(3) Condition(1) CL = 50pF RL = 500 74FCT373AT Min.(2) Max. 1.5 5.2 2 1.5 1.5 2 1.5 5 8.5 6.5 5.5 -- -- -- 74FCT373CT Min.(2) Max. 1.5 4.2 2 1.5 1.5 2 1.5 5 5.5 5.5 5 -- -- -- Unit ns ns ns ns ns ns ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY
Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW Parameter Propagation Delay Dx to Ox Propagation Delay LE to Ox Output Enable Time Output Disable Time Set-up Time HIGH or LOW, Dx to LE Hold Time HIGH or LOW, Dx to LE LE Pulse Width HIGH(3) Condition(1) CL = 50pF RL = 500 54FCT373T Min.(2) Max. 1.5 8.5 2 1.5 1.5 2 1.5 6 15 13.5 10 -- -- -- 54FCT373AT Min.(2) Max. 1.5 5.6 2 1.5 1.5 2 1.5 6 9.8 7.5 6.5 -- -- -- 54FCT373CT Min.(2) Max. 1.5 5.1 2 1.5 1.5 2 1.5 6 8 6.3 5.9 -- -- -- Unit ns ns ns ns ns ns ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested.
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IDT54/74FCT373T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
V CC 500 VIN Pulse Generator RT D.U.T . VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
50pF CL
500
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC.
tSU
tH
tREM
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
Octal link
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
Octal link
1.5V
1.5V
tSU
tH
Pulse Width
Set-Up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
Octal link
DISABLE 3V 1.5V
CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPHZ 0.3V 1.5V 0V tPLZ
0V 3.5V 0.3V VOL VOH 0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT54/74FCT373T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXX IDT XX FCT Device Type Temp. Range XX Package X Process Blank B Industrial MIL-STD-883, Class B Industrial Options Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package Thin Shrink Small Outline Package Military Options CERDIP Leadless Chip Carrier
SO PY Q PG
D L
373T 373AT 373CT 54 74
Fast CMOS Octal Transparent Latch
- 55C to +125C - 40C to +85C
DATA SHEET DOCUMENT HISTORY 6/26/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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